As it is well known, a micro-electro-mechanical system (MEMS) device is a microdevice that integrates mechanical and electrical functions in a silicon chip realized using lithographic microfabrication techniques.
The final device is typically composed of a MEMS die and optionally ASICs assembled on top of an organic substrate (e.g., a BT resin) using standard assembly processes. The assembly thus formed is then encapsulated in a resin (molding compound) using standard injection molding technologies.
In fact, it is well known that integrated circuits (IC) are fabricated on the surface of a semiconductor wafer in layers and later singulated into individual semiconductor devices, or “dice.” Since the material of a semiconductor wafer—commonly silicon—tends to be relatively fragile and brittle, dice are usually assembled into protective housings, or “packages,” before being interconnected with a printed circuit board (PCB), the package ensuring the interconnection between the dice and the board.
In the case of MEMS devices, bulk type packages are generally used, such as SO, QFN, cavity (plastic or ceramic).
Metal layers include patterns of conductive material (usually copper) that are vertically insulated from one another by alternating layers of insulating or dielectric material. Conductive traces are also separated within each layer by an insulating, or dielectric, material. Vertical, conductive tunnels called “vias” typically pass through insulating layers to form conductive pathways between adjacent conductive patterns, such vias thus providing the electrical connection between the metal layers.
Such vias are to be provided in the package substrate of a die or a MEMS device in order to ensure a correct signal transmission between different metal layers.
Commonly used in the field are land grid array (LGA) packages wherein a die is mounted on a package substrate and enclosed in a homogenous material molding compound.
The LGA package is so named because the package substrate has an array of electrical contact pads, or “lands,” arranged in a grid pattern on its underside. The lands are brought into electrical contact with the printed circuit board (PCB) generally by vias having polymer interposers, metal tracks or other electrically conductive element for contacting both the lands and the appropriate conductive portions of the PCB below. The PCB is substantially a support board for mounting the LGA/BGA packages, in connection in particular with their package substrates.
Owing to their structure, LGA packages are highly desirable in those cases where size reduction, performance and cost issues are particularly important.
The upper surface of a package substrate is surmounted by the silicon die, for example a MEMS device, which can be connected to the pads or to the bond fingers on the top metal layer of the land grid array by wire-bonding. Normally, the die is attached to the package substrate 10 with the aid of an adhesive material such as a glue or a tape.
The semiconductor devices (e.g., MEMS) can be found in a variety of relations with respect to each other on the integrated circuit, depending on the type of stacking configuration that applies. The devices can thus be found to be side by side, stacked, inversely stacked, etc.
The semiconductor device is normally encapsulated with a protecting material (normally epoxy resin), or cap or molding compound, to ensure electrical and mechanical protection, in general, as well as to protect against moisture, dust, and other external agents.
As well as constituting the mechanical support of the die or MEMS device, the package substrate also has a fundamental role from the electrical point of view.
A standard package substrate 10 is schematically shown in FIG. 1.
The substrate 10 is made of a polymeric material (for example, BT resin) core 4 and comprises a top 3a and a bottom copper layer 3b surrounding the core 4 as well as a top 2a and a bottom copper layer 2b on the copper layers 3a and 3b, in turn surrounded by a top 1a and a bottom solder-mask 1b. 
The number of layers that can be used in the composition of package substrates 10 is variable.
For a two-layer LGA/BGA substrate, standard thickness values are in the range of 180 to 300 μm, wherein the core is approximately 100 μm or 200 um, each copper layer is 12-28 μm, and each solder mask layer is approximately 25 μm in thickness.
In the example shown in FIG. 1, vias are realized by plated through holes or PTH 8 drilled in the core 4 to provide electrical connections between the two copper layers.
An alternative package substrate is shown in FIG. 2, the package substrate 10 including vias in pad or VIP 9. As it is well known, according to the via-in-pad approach, the via is directly placed on the lands of the LGA substrate. The VIP 9 are usually drilled and copper plated, and then filled with a solder mask.
Typical dimensions of vias are in the range of 100 to 200 μm in diameter.
The number of vias that are usually formed in the substrate varies according to need and, similarly, their distribution is dependent upon factors such as routing complexity, package or substrate sizes and, in general, design requirements and constraints.
Along the production line, the assembly of the package can represent quite a critical step for a sensitive electronic device, such as MEMS. The package, in fact, can undergo considerable mechanical stresses, especially during the molding step, which can lead to failure by delamination of the cap, and consequent loss of the sealing effect, which in turn affects the quality of performance, in terms of offset stability and drift of the package, upon use.
In order reduce this technical problem, the package substrate should be of a physical structure such that the metal layers are well-balanced, so that, throughout the production steps, it is less exposed to those mechanical stresses which are damaging to the package itself.
Such balancing, in fact, enables smoother assembly steps on the substrate and thus leads to the production of a package of longer durability and better long-term performance.
For this purpose, it is common, for example, to balance the copper layers by means of a copper mesh. Such meshes can have variable sizes, patterns and widths, and can be suitably chosen to match the specific requirements of the package substrate.
Other known solutions comprise package substrates having an increased thickness in order to enhance their tolerance to the production processes usually employed in the field. In this case, however, the total thickness of the package is also increased, which is obviously undesirable.
Moreover, in the case of devices that are especially sensitive to the mechanical stresses of the assembly step, in particular the molding step, such as the MEMS devices, such known solutions are still not sufficient to ensure effective balancing and an optimal final packaged device.
Ideally, a package substrate would be capable of withstanding the mechanical stresses of assembly, in particular of the molding step.